Standard, digital logic, integrated circuit or IC logic families were among the first IC parts designed and developed in the 1960s and now provide hundreds of different parts and specifications. Digital logic circuits provide basic Boolean logical functions such as an inverter, AND, NAND, OR, NOR, and Exclusive OR or XOR. Digital logic circuits also provide complex functions, such as flip flops, that are timed combinations of logic functions, and further provide other functions, such as multiplexers, used in digital logic circuitry.
Over time families of standard logic ICs were designed and developed with increasingly complex manufacturing processes, multiple logical functions, multiple different voltage, current, and timing specifications, and multiple different encapsulated packages.
Many of these logic ICs were originally designed and developed by large design teams, one part by one part, over a span of decades in the then current process technology. This design method made business sense in the early stages of the semiconductor era. However, since these logic families have become commoditized, generating new logic families with this old approach is not financially feasible.
Further, the multiple characteristics or specifications of the hundreds of logic ICs slow the delivery of logic ICs to customers or require a large inventory of logic ICs. Without an inventory of multiple logic ICs, a new customer order for specific logic ICs must be placed in the manufacturing cue with earlier orders and then wait for manufacture of a new batch of logic ICs, which slows delivery to a customer. Alternatively, completely finished and tested ICs can be available to immediately fill a customer order, but require substantial inventory of multiple ICs with multiple different specification waiting to fill unknown orders that may never occur, which is costly.
The inventory versus customer delivery time problem is accentuated by the large number of families of logic ICs and the large number of logic functions available in each family. The number of families can be as large as 40. These families provide multiple specification combinations, such as 0.8, 1.8, 2.5, 3.3, and 5 supply voltages in bipolar, CMOS, and BiCMOS technologies with overvoltage tolerant inputs and live insertion capabilities. Each family can provide multiple functions, such as buffers/line drivers, flip flops, combination logic, counters, shift registers, encoders/multiplexers, decoders/demultiplexers, gates, transceivers, level translators, phase lock loops, and bus switches.
The description in this specification has been prepared for a person skilled in this art and omits many details not necessary for understanding the disclosure. The drawings in the figures are abstract, high level representations of the circuit elements and logic functions depicted, such as gates, flip flops, multiplexers, non-volatile memory, and voltage regulators. The drawings intentionally omit details of implementation, such as individual transistors and their fabrication in a semiconductor die, to simplify the description and facilitate understanding of the disclosure. A person skilled in this art would understand the description of these abstract representations and understand the omission of more detailed structures or elements in the following description of the disclosure.
The descriptions of leads connecting bond pads to other elements omit descriptions of understood input and output circuits that couple the leads to the bond pads. Thus, the word “connect” may not in all cases mean a direct connection with no intervening circuits. Use of the word “couple” does infer that described, or other understood not described, structure may exist between the “coupled” elements. For example, a multiplexer circuit may selectively couple and uncouple an output of a logic function to a bond pad.
For example, FIGS. 1A, 1B, and 1C, respectively, depict a symbol for an inverter 100, a function table 140 for the inverter, and a plan view representation of an encapsulated, inverter integrated circuit 160.
Inverter 100 has an A input lead 102 and a Y output lead 104. Inverter 100 performs a logical function of providing a Y output that is the logical inverse of the input A. Thus a logic high or logic “H” applied to A input lead 102 results in a logic low or logic “L” output at Y output lead 104. A logic low or logic “L” applied to A input lead 102 results in a logic high or logic “H” at Y output lead 104. A logic level high, a logic high, or a logic “H” can also be described as a logic “1”, and a logic level low, a logic low, or a logic “L” can also be described as a logic “0”.
Function table 140 indicates the logical functions of inverter 100 with a column 142 for the possible logic states of the A input 102 and a column 144 for the resulting logic states of the Y output 104. Row 146 indicates that for a logic “H” on the A input, the Y output will be a logic “L”. Row 148 indicates that for a logic “L” on the A input, the Y output will be a logic “H”.
Encapsulated inverter integrated circuit or IC package 160 has a body 162 and 5 pins or terminals 164 numbered 1 through 5. Pin 1 is identified as “NC” or no connection. Pin 2 is identified as the A input 102. Pin 3 is identified as GND or the voltage ground electrical connection to the inverter. Pin 4 is identified as the Y output 104. Pin 5 is identified as Vcc or the voltage supply electrical connection to the inverter. In the figures depicting the logical functions, the voltage supply and ground connections are omitted as understood by a person of ordinary skill in this art to be necessary for the operation of the logical functions.
FIGS. 2A, 2B, and 2C, respectively, depict a symbol for a two input AND gate 200, a function table 240 for the AND gate, and a plan view representation of an encapsulated, AND gate integrated circuit 260.
AND gate 200 has an A input 202, a B input 204 and a Y output 206. AND gate 200 performs a logical function of providing a Y output that is the logical “AND” of the logic levels applied to the A input and the B input. Thus a logic “H” applied to A input 102 and a logic “H” applied to B input 104 results in a logic “H” at Y output 106. A logic “L” applied to either A input 202 or B input 204 results in a logic “L” at Y output 206.
Function table 240 indicates the logical functions of AND gate 200 with a column 242 for the possible logic states of the A input 202, a column 244 for the possible logic states of the B input 204, and a column 246 for the resulting logic states of the Y output 206. Row 248 indicates that for a logic “H” on the A input and a logic “H” on the B input, the Y output will be a logic “H”. Row 250 indicates that for a logic “L” on the A input and a do not care state or logic “X” on the B input, the Y output will be a logic “L”. Row 252 indicates that for a do not care logic state or logic “X” on the A input and a logic “L” on the B input, the Y output will be a logic “L”. The do not care logic state or logic “X” means that applying a logic “H” or a logic “L” to an input will have no effect on the result at the output.
Encapsulated AND integrated circuit or IC package 260 has a body 262 and 5 pins or terminals 264 numbered 1 through 5. Pin 1 is identified as the A input 202. Pin 2 is identified as the B input 204. Pin 3 is identified as GND or the voltage ground electrical connection to the AND gate 200. Pin 4 is identified as the Y output 206. Pin 5 is identified as Vcc or the voltage supply electrical connection to the AND gate 200.
FIGS. 3A, 3B, and 3C, respectively, depict a symbol for a NAND gate 300, a function table 340 for the NAND gate, and a plan view representation of an encapsulated, NAND gate integrated circuit 360.
NAND gate 300 has an A input 302, a B input 304 and a Y output 306. NAND gate 300 performs a logical function of providing a Y output that is the logical “NAND” or “Not AND” of the logic levels applied to the A input and the B input. Thus a logic “H” applied to A input 302 and a logic “H” applied to B input 304 results in a logic “L” output at Y output 306. A logic “L” applied to either A input 302 or B input 304 results in a logic “H” at Y output 306.
Function table 340 indicates the logical functions of NAND gate 300 with a column 342 for the possible logic states of the A input 302, a column 344 for the possible logic states of the B input 304, and a column 346 for the resulting logic states of the Y output 304. Row 348 indicates that for a logic “H” on the A input and a logic “H” on the B input, the Y output will be a logic “L”. Row 350 indicates that for a logic “L” on the A input and a logic “X” on the B input, the Y output will be a logic “H”. Row 352 indicates that for a logic “X” on the A input and a logic “L” on the B input, the Y output will be a logic “H”.
Encapsulated NAND integrated circuit or IC package 360 has a body 362 and 5 pins or terminals 364 numbered 1 through 5. Pin 1 is identified as the A input 302. Pin 2 is identified as the B input 304. Pin 3 is identified as GND or the voltage ground electrical connection to the NAND gate 300. Pin 4 is identified as the Y output 306. Pin 5 is identified as Vcc or the voltage supply electrical connection to the NAND gate 300.
FIGS. 4A, 4B, and 4C, respectively, depict a symbol for an OR gate 400, a function table 440 for the OR gate, and a plan view representation of an encapsulated, OR gate integrated circuit 460.
OR gate 400 has an A input 402, a B input 404 and a Y output 406. OR gate 400 performs a logical function of providing a Y output that is the logical “OR” of the logic levels applied to the A input and the B input. Thus a logic “H” applied to A input 402 or to B input 404 results in a logic “H” at Y output 406. A logic “L” applied to A input 402 and a logic “L” applied to B input 404 results in a logic “L” at Y output 406.
Function table 440 indicates the logical functions of OR gate 400 with a column 442 for the possible logic states of the A input 402, a column 444 for the possible logic states of the B input 404, and a column 446 for the resulting logic states of the Y output 406. Row 448 indicates that for a logic “H” on the A input and logic “X” on the B input, the Y output will be a logic “H”. Row 450 indicates that for a logic “X” on the A input and a logic “H” on the B input, the Y output will be a logic “H”. Row 452 indicates that for a logic “L” on the A input and a logic “L” on the B input, the Y output will be a logic “L”.
Encapsulated OR integrated circuit or IC package 460 has a body 462 and 5 pins or terminals 464 numbered 1 through 5. Pin 1 is identified as the A input 402. Pin 2 is identified as the B input 404. Pin 3 is identified as GND or the voltage ground electrical connection to the OR gate 400. Pin 4 is identified as the Y output 406. Pin 5 is identified as Vcc or the voltage supply electrical connection to the OR gate 400.
FIGS. 5A, 5B, and 5C, respectively depict a symbol for a NOR gate 500, a function table 540 for the NOR gate, and a plan view representation of an encapsulated, NOR gate integrated circuit 560.
NOR gate 500 has an A input 502, a B input 504 and a Y output 506. NOR gate 500 performs a logical function of providing a Y output that is the logical “NOR” or “Not OR” of the logic levels applied to the A input and the B input. Thus a logic “H” applied to A input 502 or to B input 504 results in a logic “L” at Y output 506. A logic “L” applied to A input 502 and a logic “L” applied to B input 504 results in a logic “H” at Y output 506.
Function table 540 indicates the logical functions of NOR gate 500 with a column 542 for the possible logic states of the A input 502, a column 544 for the possible logic states of the B input 504, and a column 546 for the resulting logic states of the Y output 506. Row 548 indicates that for a logic “H” on the A input and logic “X” on the B input, the Y output will be a logic “L”. Row 550 indicates that for a logic “X” on the A input and a logic “H” on the B input, the Y output will be a logic “L”. Row 552 indicates that for a logic “L” on the A input and a logic “L” on the B input, the Y output will be a logic “H”.
Encapsulated NOR integrated circuit or IC package 560 has a body 562 and 5 pins or terminals 564 numbered 1 through 5. Pin 1 is identified as the A input 502. Pin 2 is identified as the B input 504. Pin 3 is identified as GND or the voltage ground electrical connection to the NOR gate 500. Pin 4 is identified as the Y output 506. Pin 5 is identified as Vcc or the voltage supply electrical connection to the NOR gate 500.
FIGS. 6A, 6B, and 6C, respectively, depict a symbol for an EXCLUSIVE OR or XOR gate 600, a function table 640 for the EXCLUSIVE OR or XOR gate, and a plan view representation of an encapsulated, EXCLUSIVE OR or XOR gate integrated circuit 660.
XOR gate 600 has an A input 602, a B input 604 and a Y output 606. XOR gate 600 performs a logical function of providing a Y output that is the logical “EXCLUSIVE OR” of the logic levels applied to the A input and the B input. Thus a logic “L” applied to A input 602 and a logic “L” applied to B input 604 results in a logic “L” at Y output 606. A logic “H” applied to A input 602 and a logic “H” applied to B input 604 results in a logic “L” at Y output 606. A logic “H” applied to one of A input 602 or B input 604 and a logic “L” applied to the other of A input 602 or B input 604 results in a logic “H” at y output 606.
Function table 640 indicates the logical functions of XOR gate 600 with a column 642 for the possible logic states of the A input 602, a column 644 for the possible logic states of the B input 604, and a column 646 for the resulting logic states of the Y output 606. Row 648 indicates that for a logic “L” on the A input and logic “L” on the B input, the Y output will be a logic “L”. Row 450 indicates that for a logic “L” on the A input and a logic “H” on the B input, the Y output will be a logic “H”. Row 452 indicates that for a logic “H” on the A input and a logic “L” on the B input, the Y output will be a logic “H”. Row 654 indicates that for a logic “H” on the A input and logic “H” on the B input, the Y output will be a logic “L”.
Encapsulated XOR integrated circuit or IC package 660 has a body 662 and 5 pins or terminals 664 numbered 1 through 5. Pin 1 is identified as the A input 602. Pin 2 is identified as the B input 604. Pin 3 is identified as GND or the voltage ground electrical connection to the XOR gate 600. Pin 4 is identified as the Y output 606. Pin 5 is identified as Vcc or the voltage supply electrical connection to the XOR gate 600.
FIGS. 7A, 7B, and 7C, respectively, depict a symbol for a D-type flip flop 700, a function table 740 for the D-type flip flop, and a plan view representation of an encapsulated, D-type flip flop integrated circuit 760.
D-type flip flop 700 has a clock or CLK input 702, a data or D input 704 and a Y output 706. D-type flip flop 700 performs a function of providing a Y output that is the same logic level as the logic level applied to input D on a rising edge of a clock signal at CLK input 702. Thus a logic “H” applied to D input 702 at a rising edge of a clock signal applied to CLK input 702 results in a logic “H” at Y output 706. A logic “L” applied to D input 702 at a rising edge of a clock signal applied to CLK input 702 results in a logic “L” at Y output 706.
Function table 740 indicates the functions of D-type flip flop 700 with a column 742 for rising edges (indicated by up arrows ↑) of a clock signal applied to the CLK input 702 and one logic state of the clock signal at the CLK input 702, a column 744 for the possible logic states of the D input 704, and a column 746 for the resulting logic states of the Y output 706. Row 748 indicates that for a rising edge on the CLK input and logic “H” on the D input, the Y output will be a logic “H”. Row 750 indicates that for a rising edge on the CLK input and a logic “L” on the D input, the Y output will be a logic “L”. Row 752 indicates that for a logic “L” on the CLK input and a logic “X” on the D input, the Y output will be a logic “Q0” or the Y output at the previous rising edge of the clock signal at the CLK input.
Encapsulated D-type flip flop integrated circuit or IC package 760 has a body 762 and 5 pins or terminals 764 numbered 1 through 5. Pin 1 is identified as the D input 704. Pin 2 is identified as the CLK input 702. Pin 3 is identified as GND or the voltage ground electrical connection to the D-type flip flop 700. Pin 4 is identified as the Y or Q output 706. Pin 5 is identified as Vcc or the voltage supply electrical connection to the D-type flip flop 700.
FIGS. 8A, 8B, and 8C, respectively, depict a symbol for an octal D-type flip flop arrangement 800, a function table 840 for each D-type flip flop of the octal arrangement, and a plan view representation of an encapsulated, octal D-type flip flop integrated circuit 860.
Octal D-type flip flop arrangement 800 has eight D-type flip flops 802-1 through 802-8, eight data inputs, 1D input lead 804-1 through 8D input lead 804-8, one clock signal CLK input lead 806, an inverted output enable OE— input lead 808, and eight outputs, 1Q output lead 810-1 through 8Q output lead 810-8. Not all of the D-type flip flops are depicted to simplify the drawing. The lines in FIGS. 8A, 8B, and 8C, and the other figures indicate leads, wires, or some other electrical connection to, from, or between parts.
D-type flip flop 802-1 has a data input, 1D, to data input lead 804-1 and a clock input, C1, to CLK input lead 806 through buffer 812. D-type flip flop 802-8 has a data input, 8D, to data input lead 804-8 and a clock input, C8, to CLK input lead 806 through buffer 812. Thus each D-type flip flop has a separate data input, 1D through 8D, and has a common connection C1-C8 to the CLK input lead 806 through buffer 812.
D-type flip flop 802-1 has a data output, Y1, connected to output lead 1Q 810-1 through tristate output buffer 814-1. D-type flip flop 802-8 has a data output, Y8, connected to output lead 8Q 810-1 through tristate output buffer 814-8. Thus each D-type flip flop has a separate data output, Y1 through Y8, respectively connected to output leads 1Q 810-1 to 2Q 810-8 through tristate output buffers 814-1 through 814-8. Tristate output buffers 814-1 through 814-8 each have a tristate control input connected by leads to the inverted output enable OE input lead 808 through inverting buffer 814. Tristate buffers 814-1 through 814-8 in a normal condition pass the logic state at their inputs to their outputs. In a tristate condition, or Z state, these buffers block the logic state at their inputs and present an electrical open at their outputs. A logic “L” signal on the inverted output enable _OE input lead 808 provides the normal condition, and a logic “H” signal provides the tristate condition.
Each D-type flip flop 802-1 through 802-8 performs the same function as the D-type flip flop described in FIGS. 7A, 7B, and 7C. In a normal condition, each D-type flip flop performs the function of providing a Y and Q output that is the same logic level as the logic level applied to input D on a rising edge of a clock signal C1 at CLK input 806. Thus a logic “H” applied to the 1D input lead 804-1 at a rising edge of a clock signal C1 applied to CLK input lead 806 results in a logic “H” at the 1Y output and 1Q output lead 814-1. A logic “L” applied to the 1D input lead 804-1 at a rising edge of a clock signal C1 applied to CLK input lead 806 results in a logic “L” at the 1Y output and 1Q output lead 814-1.
Function table 840 indicates the functions of D-type flip flop arrangement 800 with a column 842 for the inverted output enable _OE signals applied to _OE input lead 808, a column 844 for the rising edges (indicated by up arrows ↑) and logic states of a clock signal applied to the CLK input lead 806, a column 846 for the possible logic states of the D inputs on input leads 804-1 through 804-8, and a column 848 for the resulting logic states of the Q outputs on output leads 810-1 through 810-8. Row 850 indicates that for a logic “L” on _OE, a rising edge on the CLK input and logic “H” on the D input, the Q output will be a logic “H”. Row 852 indicates that for a logic “L” on _OE, a rising edge on the CLK input and a logic “L” on the D input, the Q output will be a logic “L”. Row 854 indicates that for a logic “L” on _OE, a logic “H” or “L” on the CLK input and a logic “X” on the D input, the Q output will be a logic “Q0” or the Q output at the previous rising edge of the clock signal at the CLK input. Row 856 indicates that for a logic “H” on OE, a logic “X” on the CLK input and a logic “X” on the D input, the Q output will be a logic “Z” or a tristate condition.
Encapsulated octal D-type flip flop integrated circuit or IC package 860 has a body 862 and 20 pins or terminals 864 numbered 1 through 20. The numbered pins and functional input or output leads are identified as follows:
Pin NumberInput/Output lead1_OE21Q31D42D52Q63Q73D84D94Q10GND11CLK125Q135D146D156Q167Q177D188D198Q20Vcc
FIG. 9 depicts an integrated circuit 900 with a substrate of semiconductor material 902, core circuitry 904, and six bond pads 906-1 through 906-6. The core circuitry can be any desired circuitry including logic circuitry such as the inverter circuitry of FIG. 1A, the AND circuitry of FIG. 2A, the NAND circuitry of FIG. 3A, the OR circuitry of FIG. 4A, the NOR circuitry of FIG. 5A, the XOR circuitry of FIG. 6A, the D-type flip flop circuitry of FIG. 7A, or any other desired circuitry that has six or less inputs and outputs.
FIG. 10 depicts an integrated circuit 1000 with a substrate of semiconductor material 1002, core circuitry 1004, and eight bond pads 1006-1 through 1006-8. The core circuitry can be any desired circuitry including combinations of logic circuitry such as the inverter circuitry of FIG. 1A, the AND circuitry of FIG. 2A, the NAND circuitry of FIG. 3A, the OR circuitry of FIG. 4A, the NOR circuitry of FIG. 5A, the XOR circuitry of FIG. 6A, the D-type flip flop circuitry of FIG. 7A, or any other desired circuitry that has eight or less inputs and outputs.
FIG. 11 depicts an integrated circuit 1100 with a substrate of semiconductor material 1102, core circuitry 1104, and fourteen bond pads 1106-1 through 1106-14. The core circuitry can be any desired circuitry including combinations of logic circuitry such as the inverter circuitry of FIG. 1A, the AND circuitry of FIG. 2A, the NAND circuitry of FIG. 3A, the OR circuitry of FIG. 4A, the NOR circuitry of FIG. 5A, the XOR circuitry of FIG. 6A, the D-type flip flop circuitry of FIG. 7A, or any other desired circuitry that has fourteen or less inputs and outputs.
FIG. 12 depicts an integrated circuit 1200 with a substrate of semiconductor material 1202, core circuitry 1204, and twenty bond pads 1206-1 through 1206-20. The core circuitry can be any desired circuitry including combinations of logic circuitry such as the inverter circuitry of FIG. 1A, the AND circuitry of FIG. 2A, the NAND circuitry of FIG. 3A, the OR circuitry of FIG. 4A, the NOR circuitry of FIG. 5A, the XOR circuitry of FIG. 6A, the D-type flip flop circuitry of FIG. 7A, or any other desired circuitry that has twenty or less inputs and outputs.
FIGS. 13A, 13B, and 13C, respectively, depict a dual AND gate arrangement 1300, a function table 1340 for the dual AND gate arrangement, and a plan view representation of an encapsulated, dual AND gate integrated circuit 1360.
AND gate 1302 has a 1A input 1304, a 1B input 1306 and a 1Y output 1308. AND gate 1310 has a 2A input 1312, a 2B input 1314 and a 2Y output 1316. Each AND gate 1302 and 1310 provide the same functions as described for the AND gate 200 in FIG. 2A. Function table 1340 indicates the same logical functions of AND gates 1302 and 1310 as the AND gate 200 in FIG. 2A.
Encapsulated dual AND integrated circuit or IC package 1360 has a body 1362 and eight pins or terminals 1364 numbered 1 through 5. Pin 1 is identified as the 1A input 1304. Pin 2 is identified as the 1B input 1306. Pin 3 is identified as the 2Y output 1316. Pin 4 is indicated as the GND or the voltage ground electrical connection to the package 1360. Pin 5 is identified as the 2A input 1312. Pin 6 is identified as the 2B input 1314. Pin 6 is identified as the 1Y output 1308. Pin 8 is identified as Vcc or the voltage supply electrical connection to the package 1360.
Reducing the number of different parts that must be manufactured to supply all of these and other configurations would provide significant cost savings in inventory and reduce the time to supply customer orders.